In the known solutions, such a process makes it necessary to manually identify the number of FPGAs required to carry out the prototyping of the envisaged ASIC circuit. This is customarily carried out as follows, in accordance with the schematic illustration given in FIG. 1.
It is necessary to begin with an estimation of the FPGAs which may be a coarse estimation, for example based on the number of functional blocks that it is desired to integrate in order to create the circuit. One possibility may consist in separating each functional block into an FPGA or into a suite of several FPGAs. Alternatively, it is possible to use a synthesis tool to calculate the equivalent FPGA resources which are required.
When the necessary FPGAs have been identified, the number of necessary connections between the various FPGAs must be estimated. Here again, if an approach is used in which each functional block is an FPGA, the connections between functional blocks will be the connections between the FPGAs of the board.
It is then necessary to create the list of connections of the board which defines each FPGA and the connections between the various FPGAs. Using all of this information, it is possible to commence the process of partitionning the ASIC into several FPGAs, this making it necessary to use a synthesis tool.
In practice, it may be necessary to delete or to add FPGAs and connections between FPGAs to allow satisfactory partitioning.
In practice, such a process of establishing an ASIC circuit FPGA prototype may take up to six months, without it being certain that an optimal solution is attained.